One wafer, 200 mm in diameter and containing 72 complete VIRAM1 dice.
VIRAM1 taped out in October 2002. The design was fabricated by IBM, who sent us wafers in June 2003. After being thinned, diced, and packaged, parts were sent to ISI, who produced final boards.
One wafer, 200 mm in diameter and containing 72 complete VIRAM1 dice.
In this picture, most of the dice have at least the logo and
embedded DRAM visible. The logo is the bright corner in the
corner of each die. The embedded DRAM are the four rectangles along both
sides of each die.
Some of the dice also have vector lanes, scalar core, and vector
control logic visible. The vector lanes are four squares between the
two rows of embedded DRAM; the scalar core and vector control logic
are faint rectangles beside the logo.
In this closeup of the wafer and a die, you can see many of the
subblocks on each individual die, and even make out some of the
detail of the logo.
Another picture of the wafer.
In this picture, the die size of approximately 18 mm square is shown
in comparison to a penny.
This shows two closeups of the logo on chip, through a microscope. You
can see the top level of the power grid around the logo as parallel
lines.
The logo itself shows lines that were placed by the automatic IBM
density routines.
This is another interesting picture taken through a microscope.
The logo is in the
lower right corner of the picture.
Directly left of the logo is some logic, mostly obscured by the power grid but faintly visible. That area contains the vector control logic.
Above the logo are a few shapes that look like ovals; those are actually rectangular fuse bays for the DRAM. The DRAM is tested before the wafers are chopped up into individial dice; the DRAM is then repaired, and the working memory blocks are permanently mapped in by using lasers to blow fuses in the embedded DRAM. Because the fuses must not be obscured by higher metal layers, they are very visible.
To the left of the fuses (and eDRAM) is part of the crossbar first vector lane.
You can see wirebond terminals near the edge of the chip. At the very
edge of the chip is actually test structures placed onto the wafer
by IBM. Those are used for wafer testing and characterization,
and then are not used anymore. The wafer dicing process simply chops
through those structures and they remain, unused, on the very edge of the die.
This shows a single die and package.
The package doesn't have its leads
trimmed yet, so they are pretty long and still connected to the
tie bar. You can see the cavity in the package where the
die is placed, and the bonding terminals on the package the surround
the cavity.
In the foreground is a bonded die with the lid not yet attached
to the package. The background shows a package (before lead
trimming) and a single die.
This is the two test boards designed by ISI.
The left board is the core card. In the original setup, the core card contains a standard MIPS chip and plugs into the Malta board.
The right board is the VIRAM1 daughtercard.
In our setup, the daughtercard plugs into the new core card, which
then plugs into the standard Malta board, forming a three-board
sandwich of sorts.
This is the test setup. The Daughtercard and VIRAM1 core card are shown
out of the test machine, which is immediately next to them. To the
right of that is a networked machine that lets us control the Malta
test board via a serial connection.
This is the test machine. The Malta board is visible in the machine;
the daughtercard with
large chip labelled "VIRAM1" is in the right foreground. VIRAM1
core card is in left foreground.
The Malta board has a number of useful
test features, including an eight-character display in the
lower right corner of the board. Right now it shows "YAMON", which
is the program that lets us load (and test) other programs.
A closeup of the test machine. Standard MIPS core core is visible in
upper left corner, above of the white expansion slots.
Here's a nice straight-on picture of the actual die:
and the wafer:
